View ISP1102A_4914284.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IMPORTANT NOTICE
Dear customer, As from August 2nd 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document.
Company name - NXP B.V. is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of each page "(c) NXP B.V. 200x. All rights reserved", shall now read: "(c) ST-NXP Wireless 200x - All rights reserved". Web site - http://www.nxp.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices previously obtained by sending an email to salesaddresses@nxp.com , is now found at http://www.stnwireless.com under Contacts.
If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless
www.stnwireless.com
ISP1102A
Advanced Universal Serial Bus transceiver
Rev. 01 -- 15 February 2007 Product data sheet
1. General description
The ISP1102A Universal Serial Bus (USB) transceiver is fully compliant with Ref. 1 "Universal Serial Bus Specification Rev. 2.0". The ISP1102A can transmit and receive USB data at full-speed (12 Mbit/s). The transceiver allows USB Application-Specific Integrated Circuits (ASICs) and Programmable Logic Devices (PLDs) with power supply voltages from 1.65 V to 3.6 V to interface with the physical layer of the USB. The transceiver has an integrated 5 V-to-3.3 V voltage regulator for direct powering through USB supply line VBUS. The transceiver has an integrated voltage detector to detect the presence of the VBUS voltage (VCC(5V0)). When VCC(5V0) or VREG3V3 is lost, the DP and DM pins can be shared with other serial protocols. The transceiver is a bidirectional differential interface and is available in HBCC16 package. The transceiver is ideal for use in portable electronic devices, such as mobile phones, digital still cameras, Personal Digital Assistants (PDAs) and Information Appliances (IAs).
2. Features
I I I I I I I I I I I I I Complies with Ref. 1 "Universal Serial Bus Specification Rev. 2.0" Supports data transfer at full-speed (12 Mbit/s) Integrated 5 V-to-3.3 V voltage regulator to power through USB line VBUS VBUS voltage presence indication on pin VBUSDET VP and VM pins function in bidirectional mode, allowing pin count saving for the ASIC interface Used as USB device transceiver or USB host transceiver Stable RCV output during Single-Ended Zero (SE0) condition Two single-ended receivers with hysteresis Low-power operation Supports I/O voltage range from 1.65 V to 3.6 V 12 kV ElectroStatic Discharge (ESD) protection at the DP, DM, VCC(5V0) and GND pins Full industrial operating temperature range from -40 C to +85 C Available in HBCC16 lead-free and halogen-free package
NXP Semiconductors
ISP1102A
Advanced USB transceiver
3. Applications
I Portable electronic devices, such as: N Mobile phone N Digital still camera N Personal Digital Assistant (PDA) N Information Appliance (IA)
4. Ordering information
Table 1. Ordering information Package Name ISP1102AW HBCC16 Description Version plastic thermal enhanced bottom chip carrier; 16 terminals; body 3 x 3 x 0.65 mm SOT639-2 Type number
5. Block diagram
3.3 V VCC(IO)
VOLTAGE REGULATOR
VCC(5V0) VREG3V3 VPU3V3
1.5 k 33 (1 %)
DP VBUSDET SOFTCON OE_N RCV VP/VPO VM/VMO SUSPEND LEVEL SHIFTER DM
33 (1 %)
ISP1102A
GND
004aaa843
Fig 1. Block diagram
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
2 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
6. Pinning information
6.1 Pinning
SOFTCON
16
15
14
VCC(5V0) 13
OE_N
1
VPU3V3
VREG3V3
RCV VP/VPO VM/VMO
2 3 4
12
n.c. n.c. DP
ISP1102AW
11 10
SUSPEND
5
9
DM
004aaa844
6
VCC(IO)
7
Transparent top view
Fig 2. Pin configuration HBCC16 (top view)
6.2 Pin description
Table 2. Symbol[1] OE_N Pin description Pin 1 Type[2] I Description input for output enable (CMOS level with respect to VCC(IO), active LOW); enables the transceiver to transmit data on the USB bus input pad; push pull; CMOS RCV 2 O differential data receiver output (CMOS level with respect to VCC(IO)); driven LOW when input SUSPEND is HIGH; the output state of RCV is preserved and stable during an SE0 condition output pad; push pull; 4 mA output drive; CMOS VP/VPO 3 I/O single-ended DP receiver output VP (CMOS level with respect to VCC(IO)); for external detection of SE0, error conditions, speed of connected device; this pin also acts as drive data input VPO; see Table 3 and Table 4 bidirectional pad; push-pull input; 3-state output; 4 mA output drive; CMOS VM/VMO 4 I/O single-ended DM receiver output VM (CMOS level with respect to VCC(IO)); for external detection of SE0, error conditions, speed of connected device; this pin also acts as drive data input VMO; see Table 3 and Table 4 bidirectional pad; push-pull input; 3-state output; 4 mA output drive; CMOS SUSPEND 5 I suspend input (CMOS level with respect to VCC(IO)); a HIGH level enables low-power state while the USB bus is inactive and drives output RCV to a LOW level input pad; push pull; CMOS n.c. 6 not connected
ISP1102A_1
VBUSDET
n.c.
8
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
3 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
Table 2. Symbol[1] VCC(IO)
Pin description ...continued Pin 7 Type[2] Description supply voltage for digital I/O pins (1.65 V to 3.6 V); when VCC(IO) is not connected, the DP and DM pins are in 3-state; this supply pin is totally independent of VCC(5V0) and VREG3V3 and must never exceed the VREG3V3 voltage VBUS indicator output (CMOS level with respect to VCC(IO))
VBUSDET
8
O
* * *
When VBUS > 4.1 V, then VBUSDET = HIGH When VBUS < 3.6 V, then VBUSDET = LOW When SUSPEND = HIGH, then the VBUSDET function is invalid
Connect a 1 F-to-10 F decoupling capacitor (4.7 F capacitor is used on the ISP1102 evaluation board) output pad; push pull; 4 mA output drive; CMOS DM DP n.c. n.c. VREG3V3 9 10 11 12 13 AI/O AI/O negative USB data bus connection (analog, differential) positive USB data bus connection (analog, differential) not connected not connected internal regulator option: regulated supply voltage output (3.0 V to 3.6 V) during 5 V operation; a decoupling capacitor of at least 0.1 F is required regulator bypass option: used as a supply voltage input (3.3 V 10 %) for 3.3 V operation VCC(5V0) 14 internal regulator option: supply voltage input (4.0 V to 5.5 V); can directly be connected to USB line VBUS regulator bypass option: connect to VREG3V3 VPU3V3 15 pull-up supply voltage (3.3 V 10 %); connect an external 1.5 k resistor on DP (full-speed) This pin function is controlled by the SOFTCON input: SOFTCON = LOW -- VPU3V3 floating (high-Z); ensures zero pull-up current SOFTCON = HIGH -- VPU3V3 = 3.3 V; internally connected to VREG3V3 SOFTCON 16 I software controlled USB connection input; a HIGH level applies 3.3 V to pin VPU3V3, which is connected to an external 1.5 k pull-up resistor; this allows USB connect or disconnect signaling to be controlled by software input pad; push pull; CMOS GND exposed die pad ground supply; down bonded to the exposed die pad (heat sink); to be connected to the PCB ground
[1] [2]
Symbol names with an underscore N (for example, OE_N) indicate active LOW signals. I = input; O = output; I/O = digital input/output; AI/O = analog input/output.
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
4 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
7. Functional description
7.1 Function selection
Table 3. LOW LOW HIGH HIGH
[1] [2]
Function selection DP, DM driving or receiving receiving[1] driving high-Z[1] RCV active active inactive[2] inactive[2] VP/VPO VPO input VP output VPO input VP output VM/VMO VMO input VM output VMO input VM output Function normal driving (differential receiver active) receiving driving during suspend (differential receiver inactive) low-power state LOW HIGH LOW HIGH
SUSPEND OE_N
Signal levels on the DP and DM pins are determined by other USB devices and external pull-up or pull-down resistors. In suspend mode (SUSPEND = HIGH), the differential receiver is inactive and output RCV is always LOW. The resume signaling is detected through single-ended receivers VP/VPO and VM/VMO.
7.2 Operating functions
Table 4. VM/VMO LOW LOW HIGH HIGH Table 5. DP, DM Differential logic 0 Differential logic 1 SE0
[1]
Driving function using differential input data interface (pin OE_N = LOW) VP/VPO LOW HIGH LOW HIGH Data SE0 differential logic 1 differential logic 0 illegal state
Receiving function (pin OE_N = HIGH) RCV LOW HIGH RCV*[1] VP/VPO LOW HIGH LOW VM/VMO HIGH LOW LOW
RCV* denotes the signal level on output RCV just before the SE0 state occurs. This level is stable during the SE0 period.
7.3 Power supply configurations
The ISP1102A can be used with various power supply configurations, which can be changed dynamically. Table 7 provides an overview of the power supply configurations. Normal mode -- VCC(IO) is connected. VCC(5V0) is connected only, or VCC(5V0) and VREG3V3 are connected. For the 5 V operation, VCC(5V0) is connected to a 5 V source (4.0 V to 5.5 V). The internal voltage regulator then produces 3.3 V for USB connections. For the 3.3 V operation, both VCC(5V0) and VREG3V3 are connected to a 3.3 V source (3.0 V to 3.6 V). VCC(IO) is independently connected to a voltage source (1.65 V to 3.6 V), depending on the supply voltage of the external circuit.
ISP1102A_1 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
5 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
Sharing mode -- VCC(IO) is connected only, VCC(5V0) is < 3.6 V, and VREG3V3 is < 2.4 V. In this mode, the DP and DM pins are 3-stated and the ISP1102A allows external signals of up to 3.6 V to share the DP and DM lines. The internal circuits of the ISP1102A ensure that virtually no current (maximum 10 A) is drawn through the DP and DM lines. The power consumption through pin VCC(IO) drops to the low-power (suspended) state level. Pins VBUSDET and RCV are driven to LOW to indicate this mode. The VBUSDET function is ignored during suspend mode of the ISP1102A. Some hysteresis is built into the detection of VREG3V3 lost. Remark: Sharing mode is not possible in the regulator bypass option.
Table 6. Pin VCC(5V0) VREG3V3 VCC(IO) VPU3V3 DP, DM VP/VPO, VM/VMO[1] RCV VBUSDET OE_N, SUSPEND, SOFTCON
[1] VP/VPO and VM/VMO are bidirectional pins.
Pin states in sharing modes Sharing mode < 3.6 V < 2.4 V 1.65 V to 3.6 V input high-Z (off) high-Z LOW LOW LOW high-Z
Table 7. VCC(5V0) Connected < 3.6 V
Power supply configuration overview VCC(IO) connected connected Configuration normal mode sharing mode Special characteristics DP, DM and VPU3V3: high-Z VP/VPO and VM/VMO: driven LOW RCV: driven LOW VBUSDET: driven LOW
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
6 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
7.4 Power supply input options
The ISP1102A has two power supply input options. Internal regulator -- Pin VCC(5V0) is connected to 4.0 V to 5.5 V. The internal regulator is used to supply the internal circuitry with 3.3 V (nominal). The VREG3V3 pin becomes a 3.3 V output reference. Regulator bypass -- Pins VCC(5V0) and VREG3V3 are connected to the same supply. The internal regulator is bypassed and the internal circuitry is supplied directly from pin VREG3V3. The voltage range is 3.0 V to 3.6 V to comply with Ref. 1 "Universal Serial Bus Specification Rev. 2.0". The supply voltage range for each input option is specified in Table 8.
Table 8. Power supply input options VCC(5V0) VREG3V3 VCC(IO) supply input for digital I/O pins (1.65 V to 3.6 V) supply input for digital I/O pins (1.65 V to 3.6 V) supply input for internal regulator voltage reference output (4.0 V to 5.5 V) (3.3 V, 300 A) connected to VREG3V3 with maximum voltage drop of 0.3 V (2.7 V to 3.6 V) supply input (3.0 V to 3.6 V)
Input option Internal regulator Regulator bypass
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
7 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
8. ElectroStatic Discharge (ESD)
8.1 ESD protection
For the HBCC package, the pins that are connected to the USB connector (DP, DM, VCC(5V0) and GND) have a minimum of 12 kV ESD protection. The 12 kV measurement is limited by the test equipment. Capacitors of 4.7 F connected from VREG3V3 to GND and VCC(5V0) to GND are required to achieve this 12 kV ESD protection (see Figure 3).
RC 1 M RD 1500
charge current limit resistor
discharge resistance A
DEVICE UNDER TEST VCC(5V0) VREG3V3
HIGH VOLTAGE DC SOURCE
CS 100 pF
storage capacitor
B
4.7 F
4.7 F
GND
004aaa145
Fig 3. Human body ESD test model
8.2 ESD test conditions
A detailed report on test set up and results is available on request.
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
8 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
9. Limiting values
Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC(5V0) VCC(IO) VI Ilu Vesd Parameter supply voltage (5.0 V) IO supply voltage input voltage latch-up current VI = -1.8 V to +5.4 V
[1][2]
Conditions
Min -0.5 -0.5 -0.5 -12000 -2000 -40
Max +6.0 +4.6 100 +12000 +2000 +125
Unit V V mA V V C
VCC(IO) + 0.5 V V
electrostatic discharge voltage pins DP, DM, VCC(5V0) and GND; ILI < 3 A all other pins; ILI < 1 A storage temperature
[2]
Tstg
[1] [2]
Testing equipment limits measurement to only 12 kV. Capacitors needed on VCC(5V0) and VREG3V3 (see Section 8). Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor (Human Body Model).
10. Recommended operating conditions
Table 10. Symbol VCC(5V0) VCC(IO) VI VIA(I/O) Tj Tamb Recommended operating conditions Parameter supply voltage (5.0 V) IO supply voltage input voltage input voltage on analog I/O pins on pins DP and DM junction temperature ambient temperature Conditions Min 4.0 1.65 0 0 -40 -40 Typ 5.0 Max 5.5 3.6 VCC(IO) 3.6 +125 +85 Unit V V V V C C
11. Static characteristics
Table 11. Static characteristics: supply pins VCC(5V0) = 4.0 V to 5.5 V or V(VREG3V3) = 3.0 V to 3.6 V; VCC(IO) = 1.65 V to 3.6 V; VGND = 0 V; see Table 8 for valid voltage level combinations; Tamb = -40 C to +85 C; unless otherwise specified. Symbol V(VREG3V3) ICC Parameter voltage on pin VREG3V3 supply current Conditions internal regulator option; Iload 300 A transmitting and receiving at 12 Mbit/s; CL = 50 pF on pins DP and DM
[1][2]
Min 3.0 -
Typ 3.3 4
Max 3.6 8
Unit V mA
[3]
ICC(IO) ICC(idle) ICC(IO)static ICC(susp)
supply current on pin VCC(IO) transmitting and receiving at 12 Mbit/s idle and SE0 supply current static supply current on pin VCC(IO) suspend supply current idle: VDP > 2.7 V, VDM < 0.3 V; SE0: VDP < 0.3 V, VDM < 0.3 V idle, SE0 or suspend SUSPEND = HIGH
[3]
-
1 -
2 300 20 20
mA A A A
[4]
[4]
-
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
9 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
Table 11. Static characteristics: supply pins ...continued VCC(5V0) = 4.0 V to 5.5 V or V(VREG3V3) = 3.0 V to 3.6 V; VCC(IO) = 1.65 V to 3.6 V; VGND = 0 V; see Table 8 for valid voltage level combinations; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ICC(IO)sharing Parameter Conditions Min Typ Max 20 10 10 Unit A A A sharing mode supply current VCC(5V0) < 3.6 V on pin VCC(IO) VCC(5V0) < 3.6 V; SOFTCON = LOW; VDM = 3.6 V VCC(5V0) < 3.6 V; SOFTCON = LOW; VDP = 3.6 V 1.65 V VCC(IO) 3.6 V supply lost supply present VCC(5V0)hys VCC(IO)th supply voltage detection hysteresis (5.0 V) supply voltage detection threshold on pin VCC(IO) VCC(IO) = 1.8 V V(VREG3V3) = 2.7 V to 3.6 V supply lost supply present VCC(IO)hys VREG(3V3)th supply voltage detection hysteresis on pin VCC(IO) regulated supply voltage detection threshold (3.3 V) V(VREG3V3) = 3.3 V 1.65 V VCC(IO) V(VREG3V3); 2.7 V V(VREG3V3) 3.6 V supply lost supply present VREG(3V3)hys regulated supply voltage detection hysteresis (3.3 V) VCC(IO) = 1.8 V
[5]
Iload(sharing)DM sharing mode load current on pin DM Iload(sharing)DP VCC(5V0)th sharing mode load current on pin DP supply voltage detection threshold (5.0 V)
4.1 -
70
3.6 -
V V mV
1.4 -
0.45
0.5 -
V V V
2.4 -
0.45
0.8 -
V V V
[1] [2] [3] [4] [5]
Iload includes the pull-up resistor current through pin VPU3V3. The minimum voltage is 2.7 V in suspend mode. Maximum value characterized only, not tested in production. Excluding any load current and VPU3V3 or VSW source current to the 1.5 k and 15 k pull-up and pull-down resistors (200 A typ.). When VCC(IO) < 2.7 V, the minimum value for VREG(3V3)th = 2.0 V for supply present condition.
Table 12. Static characteristics: digital pins VCC(IO) = 1.65 V to 3.6 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Input levels VIL VIH Output levels VOL VOH LOW-level output voltage HIGH-level output voltage IOL = 100 A IOL = 2 mA IOH = 100 A IOH = 2 mA VCC(IO) - 0.15 V VCC(IO) - 0.4 V 0.15 0.4 V V V V LOW-level input voltage HIGH-level input voltage 0.6VCC(IO) 0.3VCC(IO) V V Parameter Conditions Min Typ Max Unit VCC(IO) = 1.65 V to 3.6 V
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
10 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
Table 12. Static characteristics: digital pins ...continued VCC(IO) = 1.65 V to 3.6 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Capacitance Cin Input levels VIL VIH Output levels VOL VOH LOW-level output voltage HIGH-level output voltage IOL = 100 A IOL = 2 mA IOH = 100 A IOH = 2 mA Leakage current ILI Input levels VIL VIH Output levels VOL VOH LOW-level output voltage HIGH-level output voltage IOL = 100 A IOL = 2 mA IOH = 100 A IOH = 2 mA Leakage current ILI Input levels VIL VIH Output levels VOL VOH LOW-level output voltage HIGH-level output voltage IOL = 100 A IOL = 2 mA IOH = 100 A IOH = 2 mA Leakage current ILI
[1]
Parameter input capacitance
Conditions pin to GND
Min -
Typ -
Max 10
Unit pF
Example 1: VCC(IO) = 1.8 V 0.15 V LOW-level input voltage HIGH-level input voltage 1.2 1.5 1.25
[1]
-
0.5 0.15 0.4 +1
V V V V V V A
input leakage current
-1
Example 2: VCC(IO) = 2.5 V 0.2 V LOW-level input voltage HIGH-level input voltage 1.7 2.15 1.9
[1]
-
0.7 0.15 0.4 +5
V V V V V V A
input leakage current
-5
Example 3: VCC(IO) = 3.3 V 0.3 V LOW-level input voltage HIGH-level input voltage 2.15 2.85 2.6
[1]
-
0.9 0.15 0.4 +5
V V V V V V A
input leakage current
-5
If VCC(IO) V(VREG3V3), then the leakage current will be higher than the specified value.
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
11 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
Table 13. Static characteristics: analog I/O pins DP and DM VCC(5V0) = 4.0 V to 5.5 V or V(VREG3V3) = 3.0 V to 3.6 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Input levels Differential receiver VDI VCM differential input sensitivity differential common mode voltage LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage HIGH-level output voltage off-state leakage current input capacitance driver output impedance input impedance switch-on resistance on pin VPU3V3 termination voltage for upstream port pull-up (RPU)
[3][4]
Parameter
Conditions
Min
Typ
Max
Unit
|VDP - VDM| includes VDI range
0.2 0.8
-
2.5
V V
Single-ended receiver VIL VIH Vhys Output levels VOL VOH ILZ Capacitance Cin Resistance ZDRV ZINP Rsw(VPU3V3) Termination VTERM 3.0 3.6 V steady-state drive
[2]
2.0 0.4 RL = 1.5 k to 3.6 V RL = 15 k to GND
[1]
39 -
0.8 0.7 0.3 3.6 +1 20 44 10
V V V V V A pF M
2.8 -1
Leakage current
pin to GND
34 10 -
[1] [2] [3] [4]
VOH(min) = V(VREG3V3) - 0.2 V. Includes external resistors of 33 1 % on both pins DP and DM. This voltage is available at pins VREG3V3 and VPU3V3. The minimum voltage is 2.7 V in suspend mode.
12. Dynamic characteristics
Table 14. Dynamic characteristics: analog I/O pins DP and DM VCC(5V0) = 4.0 V to 5.5 V or V(VREG3V3) = 3.0 V to 3.6 V; VCC(IO) = 1.65 V to 3.6 V; VGND = 0 V; see Table 8 for valid voltage level combinations; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tFR tFF FRFM Parameter rise time fall time Conditions CL = 50 pF to 125 pF; 10 % to 90 % of |VOH - VOL|; see Figure 4 CL = 50 pF to 125 pF; 90 % to 10 % of |VOH - VOL|; see Figure 4 Min 4 4 90 Typ Max 20 20 111.1 Unit ns ns % Driver characteristics
differential rise time/fall excluding the first transition from time matching Idle state
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
12 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
Table 14. Dynamic characteristics: analog I/O pins DP and DM ...continued VCC(5V0) = 4.0 V to 5.5 V or V(VREG3V3) = 3.0 V to 3.6 V; VCC(IO) = 1.65 V to 3.6 V; VGND = 0 V; see Table 8 for valid voltage level combinations; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VCRS Driver timing tPLH(drv) tPHL(drv) tPHZ tPLZ tPZH tPZL driver propagation delay (LOW to HIGH) driver propagation delay (HIGH to LOW) driver disable delay from HIGH level driver disable delay from LOW level driver enable delay to HIGH level driver enable delay to LOW level VPO, VMO to DP, DM; see Figure 5 and Figure 8 VPO, VMO to DP, DM; see Figure 5 and Figure 8 OE_N to DP, DM; see Figure 6 and Figure 9 OE_N to DP, DM; see Figure 6 and Figure 9 OE_N to DP, DM; see Figure 6 and Figure 9 OE_N to DP, DM; see Figure 6 and Figure 9 18 18 15 15 15 15 ns ns ns ns ns ns Parameter Conditions
[1]
Min 1.3
Typ -
Max 2.0
Unit V
output signal crossover excluding the first transition from voltage idle state; see Figure 5
Receiver timings Differential receiver tPLH(rcv) tPHL(rcv) receiver propagation delay (LOW to HIGH) receiver propagation delay (HIGH to LOW) single-ended propagation delay (LOW to HIGH) single-ended propagation delay (HIGH to LOW) DP, DM to RCV; see Figure 7 and Figure 10 DP, DM to RCV; see Figure 7 and Figure 10 DP, DM to VP/VPO, VM/VMO; see Figure 7 and Figure 10 DP, DM to VP/VPO, VM/VMO; see Figure 7 and Figure 10 15 15 ns ns
Single-ended receiver tPLH(se) 18 ns
tPHL(se)
-
-
18
ns
[1]
Characterized only, not tested. Limits guaranteed by design.
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
13 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
1.8 V logic input 0.9 V tFR, tLR VOH 90 % 90 % tFF, tLF 0V tPLH(drv) VOH 10 %
004aaa572
0.9 V
tPHL(drv)
VOL
10 %
differential data lines VOL
VCRS
VCRS
004aaa573
Fig 4. Rise time and fall time
Fig 5. Timing of VPO and VMO to DP and DM
2.0 V 0.9 V differential data lines 0.8 V VCRS tPLH(rcv) tPLH(se) VOH logic output
004aaa574
1.8 V logic 0.9 V input 0V VOH differential data lines VOL tPZH tPZL VCRS VOL + 0.3 V
VCRS tPHL(rcv) tPHL(se)
tPHZ tPLZ VOH - 0.3 V
0.9 V
0.9 V
004aaa575
VOL
Fig 6. Timing of OE_N to DP and DM
Fig 7. Timing of DP and DM to RCV, VP/VPO and VM/VMO
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
14 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
13. Test information
VPU3V3
DUT DP/DM
1.5 k 33
test point
CL
15 k
004aaa037
Load capacitance CL = 50 pF (minimum or maximum timing)
Fig 8. Load on pins DP and DM
33
test point
500
D.U.T.
DP or DM
50 pF
V
004aaa517
V = 0 V for tPZH and tPHZ V = V(VREG3V3) for tPZL and tPLZ
Fig 9. Load on pins DP and DM for enable time and disable time
test point D.U.T.
25 pF
004aaa709
Fig 10. Load on pins VM/VMO, VP/VPO and RCV
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
15 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
14. Package outline
HBCC16: plastic thermal enhanced bottom chip carrier; 16 terminals; body 3 x 3 x 0.65 mm SOT639-2
b D B A f terminal 1 index area E
vMCAB wMC vMCAB wMC
b1
b3
vMCAB wMC
b2 detail X
vMCAB wMC
e1 Dh e 5 9 y1 C
C y
e e4 1/2 e4 Eh e2
1 16 1/2 e3 e3
13 X A2 A A1
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 0.8 A1 0.10 0.05 A2 0.7 0.6 b 0.33 0.27 b1 0.33 0.27 b2 0.38 0.32 b3 0.38 0.32 D 3.1 2.9 Dh 1.45 1.35 E 3.1 2.9 Eh 1.45 1.35 e 0.5 e1 2.5 e2 2.5 e3 2.45 e4 2.45 f 0.23 0.17 v 0.08 w 0.1 y 0.05 y1 0.2
OUTLINE VERSION SOT639-2
REFERENCES IEC JEDEC MO-217 JEITA
EUROPEAN PROJECTION
ISSUE DATE 01-11-13 03-03-12
Fig 11. Package outline SOT639-2 (HBCC16)
ISP1102A_1 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
16 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
15. Packing information
The ISP1102AW (HBCC16 package) is delivered on a Type A carrier tape, see Figure 12. The tape dimensions are given in Table 15. The reel diameter is 330 mm. The reel is made of polystyrene (PS) and is not designed for use in a baking process. The cumulative tolerance of 10 successive sprocket holes is 0.02 mm. The camber must not exceed 1 mm in 100 mm.
4
A0
K0
W
B0
P1
type A
direction of feed
4
A0
K0
W
B0
elongated sprocket hole
P1
type B
direction of feed
004aaa728
Fig 12. Carrier tape dimensions Table 15. A0 B0 K0 P1 W Type A carrier tape dimensions for the ISP1102AW Value 3.3 3.3 1.1 8.0 12.0 0.3 Unit mm mm mm mm mm
Dimension
16. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
17 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 16.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 13) than a PbSn process, thus reducing the process window
ISP1102A_1 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
18 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 16 and 17
Table 16. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 17. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13.
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 13. Temperature profiles for large and small components
ISP1102A_1 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
19 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
17. Abbreviations
Table 18. Acronym ASIC CMOS ESD HBM SE0 USB Abbreviations Description Application-Specific Integrated Circuit Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Human Body Model Single-Ended Zero Universal Serial Bus
18. References
[1] [2] Universal Serial Bus Specification Rev. 2.0 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) (JESD22-A114D)
19. Revision history
Table 19. Revision history Release date 20070215 Data sheet status Product data sheet Change notice Supersedes Document ID ISP1102A_1
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
20 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
20. Legal information
20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
20.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
21. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
21 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
22. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .3 Function selection . . . . . . . . . . . . . . . . . . . . . . .5 Driving function using differential input data interface (pin OE_N = LOW) . . . . . . . . . . . . . . .5 Receiving function (pin OE_N = HIGH) . . . . . . .5 Pin states in sharing modes . . . . . . . . . . . . . . .6 Power supply configuration overview . . . . . . . . .6 Power supply input options . . . . . . . . . . . . . . . .7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .9 Recommended operating conditions . . . . . . . . .9 Static characteristics: supply pins . . . . . . . . . . .9 Static characteristics: digital pins . . . . . . . . . . .10 Static characteristics: analog I/O pins DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Dynamic characteristics: analog I/O pins DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Type A carrier tape dimensions for the ISP1102AW . . . . . . . . . . . . . . . . . . . . . . . . . . .17 SnPb eutectic process (from J-STD-020C) . . .19 Lead-free process (from J-STD-020C) . . . . . .19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .20 Revision history . . . . . . . . . . . . . . . . . . . . . . . .20
continued >>
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
22 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
23. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin configuration HBCC16 (top view) . . . . . . . . . .3 Human body ESD test model. . . . . . . . . . . . . . . . .8 Rise time and fall time . . . . . . . . . . . . . . . . . . . . .14 Timing of VPO and VMO to DP and DM . . . . . . .14 Timing of OE_N to DP and DM . . . . . . . . . . . . . .14 Timing of DP and DM to RCV, VP/VPO and VM/VMO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Load on pins DP and DM. . . . . . . . . . . . . . . . . . .15 Load on pins DP and DM for enable time and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Load on pins VM/VMO, VP/VPO and RCV . . . . .15 Package outline SOT639-2 (HBCC16). . . . . . . . .16 Carrier tape dimensions. . . . . . . . . . . . . . . . . . . .17 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
continued >>
ISP1102A_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 15 February 2007
23 of 24
NXP Semiconductors
ISP1102A
Advanced USB transceiver
24. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 8 8.1 8.2 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 19 20 20.1 20.2 20.3 20.4 21 22 23 24 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 5 Function selection. . . . . . . . . . . . . . . . . . . . . . . 5 Operating functions. . . . . . . . . . . . . . . . . . . . . . 5 Power supply configurations . . . . . . . . . . . . . . . 5 Power supply input options . . . . . . . . . . . . . . . . 7 ElectroStatic Discharge (ESD) . . . . . . . . . . . . . 8 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . 8 ESD test conditions . . . . . . . . . . . . . . . . . . . . . 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9 Recommended operating conditions. . . . . . . . 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 12 Test information . . . . . . . . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Packing information. . . . . . . . . . . . . . . . . . . . . 17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Introduction to soldering . . . . . . . . . . . . . . . . . 18 Wave and reflow soldering . . . . . . . . . . . . . . . 18 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 February 2007 Document identifier: ISP1102A_1

▲Up To Search▲

Price & Availability of ISP1102A

	To Download ISP1102A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .